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Application Note 130 Cyrix III CPU Layout Guidelines for 133 MHz Bus Operation Cyrix Processors REVISION HISTORY Date 3/31/99 3/29/99 Version 0.3 0.2 Revision Page 4 Added paragraph under Introduction. Removed notes 3 and 4 from Table 3. Restored subscripts on page 7. Minor typos corrected on page 27. Initial Version C:\documentation\joshua\appnotes\cIII_layout.fm 2/18/99 0.1 Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 Introduction Printed Circuit Board Stack-Up GTL+ Bus Timing Analysis Clock Layout Recommendations GTL+ Layout Recommendations Differences between Cyrix III and IntelTM CeleronTM Design Guides 4 5 7 13 17 27 Cyrix Application Note 130 - Cyrix III Layout Guideline for 133 MHz Operation 3 APPLICATION NOTE 130 Cyrix III Layout Guideline for 133 MHz Operation 1 Introduction The Cyrix III processor is a next generation Cyrix processor. Cyrix III employs a Socket 370 package, P6 bus protocol and operates with front side bus speeds of 66 MHz, 100 MHz, and 133 MHz. The Cyrix III processor system bus uses GTL+ signaling interface. The objective of this layout guideline is to provide the system designer with the information needed to achieve stable operation with 133 MHz front side bus. A Cyrix III IBIS model is available if the system designer would like to verify his design, but signal integrity analysis is not a requirement if the design falls within the specifications of this guideline. This document is to serve as a reference design to help new board designers meet the 133 MHz specification. The Guidelines in this document are for reference only, and are not a requirement for Cyrix motherboard certification. 4 Cyrix Application Note 130 - Cyrix III Layout Guideline for 133 MHz Operation 2. Printed Circuit Board Stack-Up Either a four-layer or six-layer stack-up can be used. In either case, it is important to control the characteristic impedance to be 60 ohms within +/-10% for a 6 mil-wide trace. This characteristic impedance improves signal integrity in many respects. Firstly, it improves signal integrity because it is close to the value of the termination, 56 ohms. Secondly, it reduces overshoots and undershoots. Table 1 and Figure 1 describes a four-layer stack-up which would meets the characteristic impedance requirement: S TACK-U P P A RAMETER V ALUE Height of Outer Dielectric Dielectric constant Microstrip Base Cu Thickness Microstrip Plating Cu Thickness Power Plane Cu Thickness Zo Typical 4.5 mil 4.5 0.5 oz. 0.5 oz. 1 oz. 60 ohms Table 1. Recommended Four Layer Stack-Up Parameters 1 oz. Cu 4.5 mil prepeg, r =4.5 Power Plane 1 oz. Cu 48 mil core,r=4.5 Ground Plane 1 oz. Cu 4.5 mil prepeg, r =4.5 1 oz. Cu Figure 1. Recommended Four Layer Stack-Up 62 mils Cyrix Application Note 130 - Cyrix III Layout Guideline for 133 MHz Operation 5 Table 2 and Figure 2 describe the recommended six layer stack-up which meets the characteristic impedance requirements. S TAC K-U P P ARAMETER V ALUE Height of Outer Dielect